High-density interconnect (HDI) design has become the default approach for modern electronics that demand compact form factors, high signal density, and reliable high-speed performance. From automotive camera modules and medical wearables to telecom infrastructure and aerospace telemetry, designers are increasingly working with fine-pitch ball-grid arrays, blind and buried vias, and complex layer stacks. HDI is not simply a scaled-down version of conventional PCB layout. It requires a different CAD workflow, a tighter set of design rules, and closer collaboration with fabrication partners. For a broader look at the overall process, How to Design for HDI PCB Using CAD Software provides tool-specific guidance that can complement the engineering workflow discussed here.
1. Building the Right HDI Stackup and CAD Constraints
Successful HDI design begins long before the first trace is routed. In modern CAD software, the layer stack manager is where the physical architecture of the board is defined, and this step is especially critical for HDI. Unlike a conventional through-hole PCB, an HDI board uses sequential lamination to create multiple sub-assemblies that are later bonded together. A common stackup is referred to as 1+N+1 or 2+N+2, where the number indicates how many microvia layers are placed on either side of a standard core. For example, a 2+N+2 stackup has two sequential buildup layers on the top, two on the bottom, and a conventional multilayer core in the middle.
Your CAD tool must reflect this construction accurately. If the stackup does not define which layer pairs are valid for microvias, buried vias, and through-hole vias, the router may place vias that cannot be manufactured. Most professional tools allow designers to create via spans such as layer 1 to layer 2 or layer 1 to layer 3, but those spans must match the lamination sequence. A microvia from layer 1 to layer 3 may be possible only after a specific sequential lamination step, and it will typically require a larger capture pad or a stacked microvia structure. Without an accurate stackup definition, even a visually clean layout can be rejected by the fabricator.
Design rules should also be established early. HDI boards commonly use laser-drilled microvias with diameters around 0.1 mm, and an aspect ratio close to 1:1 is preferred for reliable plating. Capture pads are typically 0.25 mm or smaller, while target pads may be slightly larger to account for layer-to-layer registration. Trace and space values often range from 75 µm to 50 µm depending on the HDI class. Setting these constraints in the CAD tool before floorplanning prevents the router from generating geometries that cannot be wet-processed or laser-drilled. It is also important to define different net classes for impedance-controlled signals, power distribution, and general routing so that clearance and width rules can be applied automatically.
Material selection matters as much as copper geometry. Many HDI stackups use resin-coated copper or low-CTE prepregs in the buildup layers to reduce Z-axis expansion and improve microvia reliability. In the CAD stackup editor, the dielectric thickness and material type should be documented clearly because impedance calculations and insertion loss predictions depend on those values. A well-defined stackup also helps the fabricator identify potential warp and copper-balance issues. HDI panels are often thin, and unbalanced copper distribution can cause dimensional instability during lamination. Adding copper thieving or fill in the CAD design can improve manufacturability without affecting signal performance if done carefully.
2. Via Architecture, BGA Fanout, and High-Speed Routing Rules
Via architecture is the heart of HDI PCB design. In conventional PCB layout, a through-hole via is a simple solution for layer transitions, but it consumes routing space on every layer and blocks BGA breakout channels. HDI replaces this with microvias, buried vias, and via-in-pad structures. The padstack editor in your CAD tool should define each via type separately. A microvia may have a laser-drilled hole of 0.1 mm, a capture pad of 0.25 mm on the outer layer, and a target pad of 0.2 mm on the next layer. A buried via may be larger, such as 0.2 mm, and span layers 2 to 5 inside the board. Each via type must be assigned to the correct layer span, otherwise the design will contain impossible structures.
For fine-pitch BGA packages, via-in-pad is often mandatory. A 0.5 mm pitch BGA leaves almost no room for a traditional dog-bone fanout. Instead, the microvia is placed directly under the SMT pad, filled and plated over, allowing the signal to escape to an inner layer immediately. CAD tools require a specific padstack definition for via-in-pad, including the fill and cap type. Some tools also require the pad to be marked as a via-in-pad component so that the solder mask opening is suppressed and the surface remains flat enough for assembly. A 0.8 mm pitch BGA may still use a conventional dog-bone fanout, but even then, microvias can save significant board area and reduce stub length.
Routing high-speed signals in HDI requires more than just meeting length constraints. Differential pairs such as USB, PCIe, Ethernet, or MIPI need their impedance maintained across layer transitions. The CAD constraint manager should set the appropriate line width and spacing for 85 ohm or 100 ohm differential impedance based on the selected dielectric materials and copper thickness. When a differential pair changes layers through a microvia, the return current must also have a nearby return path via. Without a return via, the signal may couple into unintended structures and cause SI problems. In dense HDI layouts, placing return vias next to signal layer transitions is a critical step that should be part of the routing routine.
Stacked and staggered microvias represent two different strategies for connecting multiple buildup layers. Stacked microvias are placed directly on top of each other through sequential layers, creating a continuous vertical path. Staggered microvias are offset from layer to layer, which can reduce mechanical stress but consumes more routing area. The choice affects reliability, routing density, and fabrication cost. Some CAD tools allow you to define these structures as macros or via groups, making it easier to replicate the same via arrangement across a BGA field. For the densest designs, any-layer HDI may be used, where every layer transition is made with a microvia and there is no traditional through-hole via. This approach maximizes routing flexibility but requires advanced fabrication capability and accurate CAD definitions.
3. DFM Validation and Preparing CAD Data for HDI Fabrication
Design for manufacturability is not an optional final check in HDI; it is a continuous process that should run alongside layout. Modern CAD tools include rule-checking engines that can validate via spans, annular ring minimums, solder mask clearances, and drill-to-copper distances. For HDI, the most common DFM failures involve inadequate annular rings on microvias, insufficient solder mask dams between a via-in-pad and an adjacent SMT pad, and invalid layer spans. A solder mask dam of less than 75 µm may lead to solder bridging during assembly, while a microvia annular ring below the fabricator’s limit can cause breakout and unreliable plating. Running DRC with the correct manufacturer rules prevents these issues before files are sent out.
Microvia reliability depends heavily on how the via is filled and plated. In the CAD data, the via type should include a note or attribute that specifies whether the microvia is filled with conductive or non-conductive epoxy and plated over with copper. This is especially important for via-in-pad structures, where the surface must be soldered. If the fill type is not specified, the assembler may receive a board with surface depressions, which can trap flux or gas and create voiding. Many fabricators also recommend setting a maximum microvia aspect ratio of 1:1 or slightly higher for laser drilling, and this value should be reflected in the CAD padstack definitions.
Output data formats have evolved, and HDI designs benefit from using ODB++ or IPC-2581 instead of a simple Gerber package. These formats carry netlists, layer stackups, padstack definitions, and drill information in a structured way. If Gerber files are required, they should include separate layers for each blind, buried, and through-hole drill span. The fabrication notes should clearly state the HDI class, lamination sequence, microvia diameter, target pad sizes, impedance requirements, and material preferences. A separate stackup drawing is also helpful because it shows the fabricator how the CAD tool expects the sub-laminations to be arranged.
Working with an HDI-capable fabricator early in the design cycle is one of the most effective ways to reduce re-spins. Many manufacturers can provide a DFM checklist or a set of recommended padstack values before routing begins. This is particularly useful for mixed-technology boards that combine HDI with high-frequency materials, flex or rigid-flex sections, or heavy copper layers. In one common scenario, a compact automotive camera module using a 0.5 mm pitch BGA may require a six-layer any-layer HDI stackup with 100 µm microvias on the outer layers, 150 µm buried vias in the core, and 75 µm trace and space throughout. The CAD file must capture all of these details exactly, because the fabricator’s laser drill, plating line, and registration system will be programmed directly from that data. A well-documented CAD database is therefore not just a layout deliverable; it is the single source of truth for manufacturing a reliable HDI PCB.
A Dublin journalist who spent a decade covering EU politics before moving to Wellington, New Zealand. Penny now tackles topics from Celtic mythology to blockchain logistics, with a trademark blend of humor and hard facts. She runs on flat whites and sea swims.